1. Field of the Invention
This invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit constructed by forming a plurality of functional blocks including a CPU block on a single semiconductor chip.
2. Description of the Related Art
Conventionally, in a composite IC or LSI having a plurality of functional blocks including a CPU block, a data bus of the CPU is directly connected to input/output terminals of the composite IC or LSI, or it is connected through resistors serving as bus buffers to the input/output terminals. An example of the former is shown in FIG. 8, while an example of the latter is shown in FIG. 9.
In the composite LSI of FIG. 8, a data bus 102 of a CPU 101 is directly connected to input/output terminals 104 of a composite LSI 103. Reference numeral 105 denotes an output terminal for outputting a read signal RD through a buffer 107, and reference numeral 106 denotes a functional block other than the CPU.
On the other hand, in the composite LSI of FIG. 9, signal lines of the data bus 102 of the CPU 101 are connected through resistors r to the input/output terminals 104.
In the LSI of FIG. 8, external noise directly enters the CPU 101, which causes a problem that the LSI can not maintain sufficient electrical reliability. A problem of the LSI of FIG. 9, on the other hand, is concerned with an inevitable delay of signals traveling on the data bus 102. More specifically, it is difficult to set the resistance of the resistors r to a value suitable to every case. Further, since signals are attenuated by the resistors r, the data bus driving capability is reduced.
Therefore, the object of the present invention is to provide a semiconductor integrated circuit capable of preventing such entry of external noise without posing problems of signal propagation delay and bus driving capability decrease.
The above object of the present invention can be achieved by a data bus control circuit for a semiconductor integrated circuit having input/output terminals for data exchange with the outside and constructed by forming a plurality of functional blocks including a CPU on a single semiconductor chip, said data bus control circuit comprising a bi-directional bus buffer for connecting a data bus which is connected to said CPU with said input/output terminals, and means for determining a signal propagation direction of said bus buffer according to a level of a read signal outputted from said CPU.
In a semiconductor integrated circuit using the data bus control circuit according to the present invention, the data bus of the CPU is connected to external devices through the bi-directional bus buffer. This arrangement makes it difficult for external noise to enter the data bus, so that the electrical reliability of the semiconductor integrated circuit is substantially improved. Further, in this semiconductor integrated circuit, there is not the problem of delay in signal propagation which will occur when resistors are used as the bus buffer nor the problem of decrease in the bus driving capability.
Furthermore, the data bus control circuit according to the present invention has a simple construction and can be used for any kind of composite semiconductor integrated circuit. Therefore, time and labor required to study how to best treat the data bus for different systems are not necessary which improves development efficiency.
Further objects and advantages of the present invention will be apparent from the following description with reference being had to the accompanying drawings wherein preferred embodiments of the present invention are clearly shown.